Table 3. ADSP-21371 Internal Memory Space
IOP Registers 0x0000 0000–0x0003 FFFF
Extended Precision Normal or
Long Word (64 bits)
BLOCK 0 ROM
0x0004 0000–0x0004 7FFF
Reserved
0x0004 8000–0x0004 BFFF
BLOCK 0 RAM
0x0004 C000–0x0004 CFFF
Reserved
0x0004 D000–0x0004 FFFF
BLOCK 1 ROM
0x0005 0000–0x0005 7FFF
Reserved
0x0005 8000–0x0005 BFFF
BLOCK 1 RAM
0x0005 C000–0x0005 CFFF
Reserved
0x0005 D000–0x0005 FFFF
BLOCK 2 RAM
0x0006 0000–0x0006 0FFF
Reserved
0x0006 1000–0x0006 FFFF
BLOCK 3 RAM
0x0007 0000–0x0007 0FFF
Reserved
0x0007 1000–0x0007 FFFF
Instruction Word (48 bits)
BLOCK 0 ROM
0x0008 0000–0x0008 AAA9
Reserved
0x0008 AAAA–0x0008 FFFF
BLOCK 0 RAM
0x0009 0000–0x0009 1554
Reserved
0x0009 1555–0x0009 FFFF
BLOCK 1 ROM
0x000A 0000–0x000A AAA9
Reserved
0x000A AAAA–0x000A FFFF
BLOCK 1 RAM
0x000B 0000–0x000B 1554
Reserved
0x000B 1555–0x000B FFFF
BLOCK 2 RAM
0x000C 0000–0x000C 1554
Reserved
0x000C 1555–0x000D FFFF
BLOCK 3 RAM
0x000E 0000–0x000E 1554
Reserved
0x000E 1555–0x000F FFFF
Normal Word (32 bits)
BLOCK 0 ROM
0x0008 0000–0x0008 FFFF
Reserved
0x0009 0000–0x0009 7FFF
BLOCK 0 RAM
0x0009 8000–0x0009 9FFF
Reserved
0x0009 A000–0x0009 FFFF
BLOCK 1 ROM
0x000A 0000–0x000A FFFF
Reserved
0x000B 0000–0x000B 7FFF
BLOCK 1 RAM
0x000B 8000–0x000B 9FFF
Reserved
0x000B A000–0x000B FFFF
BLOCK 2 RAM
0x000C 0000–0x000C 1FFF
Reserved
0x000C 2000–0x000D FFFF
BLOCK 3 RAM
0x000E 0000–0x000E 1FFF
Reserved
0x000E 2000–0x000F FFFF
Short Word (16 bits)
BLOCK 0 ROM
0x0010 0000–0x0011 FFFF
Reserved
0x0012 0000–0x0012 FFFF
BLOCK 0 RAM
0x0013 0000–0x0013 3FFF
Reserved
0x0013 4000–0x0013 FFFF
BLOCK 1 ROM
0x0014 0000–0x0015 FFFF
Reserved
0x0016 0000–0x0016 FFFF
BLOCK 1 RAM
0x0017 0000–0x0017 3FFF
Reserved
0x0017 4000–0x0017 FFFF
BLOCK 2 RAM
0x0018 0000–0x0018 3FFF
Reserved
0x0018 4000–0x001B FFFF
BLOCK 3 RAM
0x001C 0000–0x001C 3FFF
Reserved
0x001C 4000–0x001F FFFF
external code, executing exclusively from internal ROM. Addi-
tionally, the processor is not freely accessible via the JTAG port.
Instead, a unique 64-bit key, which must be scanned in through
the JTAG or Test Access Port will be assigned to each customer.
The device will ignore a wrong key. Emulation features and
external boot modes are only available after the correct key is
scanned.
FAMILY PERIPHERAL ARCHITECTURE
The ADSP-21371/ADSP-21375 family contains a rich set of
peripherals that support a wide variety of applications, includ-
ing high quality audio, medical imaging, communications,
military, test equipment, 3D graphics, speech recognition, mon-
itor control, imaging, and other applications.
External Port
The external port on the ADSP-21371/ADSP-21375 SHARC
processors provide a high performance, glueless interface to a
wide variety of industry-standard memory devices. The 32-bit
wide bus (ADSP-21371) may be used to interface to synchro-
nous and/or asynchronous memory devices through the use of
its separate internal memory controllers: the first is an SDRAM
controller for connection of industry-standard synchronous
DRAM devices and DIMMs (dual inline memory module),
while the second is an asynchronous memory controller
intended to interface to a variety of memory devices. Four
memory select pins enable up to four separate devices to coexist,
supporting any desired combination of synchronous and asyn-
chronous device types.
Rev. D | Page 6 of 56 | April 2013
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